I haven’t really dived into the IEEE standards here, but this is a real thing and not purely marketing. It is the resolution of the lithography. Due to the higher clock speeds and current resolutions, the capacitance and inductance of the elements set the size of transistors and routing, rather than just how small you can pattern them. So it is not directly increasing transistor density and processing power, but it means that you are patterning elements more accurately to what you designed and have less variation element to element. Meaning that things can be optimized and more consistent.